1. Field of the Invention
The invention relates generally to interfaces between data producing circuits and data consuming circuits and more specifically relates to improved methods and apparatus for translating data formats between such producer and consumer circuits.
2. Related Patents
This patent application is related to U.S. patent application Ser. No. 12/247,785 filed herewith and entitled APPARATUS AND METHODS FOR CAPTURE OF FLOW CONTROL ERRORS IN CLOCK DOMAIN CROSSING DATA TRANSFERS which is hereby incorporated by reference.
3. Discussion of Related Art
It is common in electronics that a first circuit (a producer circuit) generates data signals to be applied to a second circuit (a consumer circuit). Such producer and consumer circuits often operate in accordance with a digital clock signal to trigger and pace the data exchange. In many electronic circuit applications the producer and consumer circuits operate in different clock domain—i.e., based on different frequency clock signals. For example, an I/O interface circuit may produce data for consumption by a processor (coupled through an interface bus). The I/O producer circuit may operate at a clock frequency relating to the I/O device or network for which it serves as an interface while the host system processor bus consumer circuit may operate at a clock frequency related to the operating speed and specifications of the interface bus logic. Exchanges between such producer/consumer circuits may be referred to as a cross-domain transfer in reference to the need to operate each circuit in a separate clock domain.
In such cross-domain transfers it is common to use a first in first out (FIFO) memory device as a speed matching or elasticity buffer to allow the producer to produce data at its designed speed while the consumer circuit consumes the data at its designed speed. In addition, it is often necessary in such application circuit designs that translation logic may be added to translate the format of data and control signals generated by the consumer circuit into an appropriate format for consumption by the consumer circuit. Even where the producer and consumer circuits operate in the same clock domain (often still using a FIFO coupling then to provide buffer elasticity), it is often required that signals produced by the consumer circuit be translated into an appropriate signal format for the consumer circuit to consume. The translation may include data and associated control signals generated by the producer and used by the consumer. To implement such a translation, present designs add translation logic to the consumer circuit so that the consumer will receive data (and related control signals) from the FIFO in the format that it is expecting.
If multiple producer circuits are used to send information to a single consumer circuit, the signals from each producer circuit must be converted into the correct format to match the consumer circuit's interface. Either each producer circuit must have knowledge of the consumer circuit's control interface and have additional logic to make the translation, or the consumer circuit must have knowledge of every possible producer circuit's interface and translate the signals to the correct format.
Performing the conversion in each consumer circuit relies on the consumer having knowledge of the signal interface used by each associated producer circuit that may transfer information to the consumer. This can result in duplicated logic if multiple producer circuits which use the same control interface are used since the translation logic is present in each instance of the consumer circuit. Likewise, placing the translation logic in the producer circuit requires the producer circuit to have knowledge of the control interface of every consumer circuit which may be added to the system.
Thus it is an ongoing challenge to reduce the complexity of an application circuit having producer circuits coupled with consumer circuits in data transfer applications where data format translations are required for signals exchanged between the circuits.